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this is information on a product in full production. april 2014 docid026152 rev 1 1/32 TS2012EI filter-free flip chip st ereo 2 x 2.5 w class d audio power amplifier datasheet - production data features ? operates from v cc = 2.5 to 5.5 v ? dedicated standby mode active low for each channel ? output power per channel: 1.15 w at 5 v or 0.63 w at 3.6 v into 8 ? with 1% thd+n max. ? output power per channel: 1.85 w at 5 v into 4 ? with 1% thd+n max. ? output short-circuit protection ? four gain setting steps: 6, 12, 18, 24 db ? low current consumption ? pssr: 63 db typ. at 217 hz. ? fast startup phase: 7.8 ms ? thermal shutdown protection ? flip chip 16 bump lead-free package applications ? cellular phones ? pda description the TS2012EI is a fully-differential stereo class d power amplifier able to drive up to 1.15 w into an 8 ? load at 5 v per channel. it achieves better efficiency compared to typical class ab audio amps. the device has four differ ent gain settings utilizing two digital pins: g0 and g1. pop and click reduction circuitry provides low on/off switch noise while allowing the device to start within 8 ms. two standby pins (active low) allow each channel to be switched off separately. the TS2012EI is available in a flip chip 16 bump lead-free package. g1 inl+ lin+ lin- rin- rin+ pvcc g1 g0 avcc lout+ stdbyr agnd rout+ rout- pgnd stdbyl lout- g1 inl+ lin+ lin- rin- rin+ pvcc g1 g0 avcc lout+ stdbyr agnd rout+ rout- pgnd stdbyl lout- flip chip 16 pin connection (top view) table 1. device summary order code temperature range package packing marking TS2012EIjt - 40 c to +85 c flip chip 16 tape and reel k0 www.st.com
contents TS2012EI 2/32 docid026152 rev 1 contents 1 absolute maximum ratings and operating c onditions . . . . . . . . . . . . . 3 2 typical application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.1 electrical characteristics tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.2 electrical characteristic curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.1 differential configuration principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.2 gain settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.3 common mode feedback loop limi tations . . . . . . . . . . . . . . . . . . . . . . . . 21 4.4 low frequency response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.5 decoupling of the circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.6 wake-up time (t wu ) and shutdown time (t stby ) . . . . . . . . . . . . . . . . . . . . 23 4.7 consumption in shutdown mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.8 single-ended input configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.9 output filter considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.10 short-circuit protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.11 thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
docid026152 rev 1 3/32 TS2012EI absolute ma ximum ratings and operating conditions 32 1 absolute maximum ratings and operating conditions table 2. absolute maximum ratings symbol parameter value unit v cc supply voltage (1) 1. all voltage values are measured with respect to the ground pin. 6v v in input voltage (2) 2. the magnitude of the input signal must never exceed v cc + 0.3 v / gnd - 0.3 v. gnd to v cc v t oper operating free air temperature range -40 to + 85 c t stg storage temperature -65 to +150 c t j maximum junction temperature 150 c r thja thermal resistance junction to ambient (3) 3. the device is protected in case of over te mperature by a thermal shutdown active at 150c. 200 c/w p d power dissipation internally limited (4) 4. exceeding the power derating curves during a long period will cause abnormal operation. esd hbm: human body model (5) 5. human body model: 100 pf discharged through a 1.5 k ?? resistor between two pins of the device, done for all couples of pin combinati ons with other pins floating. 2kv mm: machine model (6) 6. machine model: a 200 pf cap is charged to the sp ecified voltage, then discharged directly between two pins of the device with no external se ries resistor (internal resistor < 5 ? ), done for all couples of pin combinations with other pins floating. 200 v latch-up latch-up immunity 200 ma v stby standby pin maximum voltage gnd to v cc v lead temperature (soldering, 10sec) 260 c output short-circuit protection (7) 7. implemented short-circuit protection protects th e amplifier against damage by short-circuit between positive and negative outputs of each channel and between outputs and ground.
absolute maximum ratings and operating conditions TS2012EI 4/32 docid026152 rev 1 table 3. operating conditions symbol parameter value unit v cc supply voltage 2.5 to 5.5 v v in input voltage range gnd to v cc v v ic input common mode voltage (1) 1. i v oo i ? 40 mv max with all differential gains except 24 db. for 24 db gain, input decoupling capacitors are mandatory. gnd+0.5v to v cc -0.9v v v stby standby voltage input (2) device on device in standby (3) 2. without any signal on standby pin, t he device is in standby (internal 300 k ? +/-20% pull-down resistor). 3. minimum current consumption is obtained when v stby = gnd. 1.4 ?? v stby ? v cc gnd ? v stby ? 0.4 v r l load resistor ? 4 ? v ih go, g1 - high level input voltage (4) 4. between g0, g1pins and gnd , there is an internal 300 k ? (+/-20%) pull-down resistor. when pins are floating, the gain is 6 db. in full standby (left and right channels off), these re sistors are disconnected (hiz input). 1.4 ?? v ih ? v cc v v il go, g1 - low level input voltage gnd ? v il ? 0.4 v r thja thermal resistance junction to ambient (5) 5. with a 4-layer pcb. 90 c/w
docid026152 rev 1 5/32 TS2012EI typical application 32 2 typical application figure 1. typical application schematics ts2012 15 h ? 2 f ? 2 f ? 15 h ? 30 h ? 1 f ? 1 f ? 30 h ? load 4 lc output filter 8 lc output filter ? ? left speak er right speaker cin cin left in+ input capacitors are optional left in- differential left input cin cin right in+ right in- differential right input standby control vcc cs 1 1uf cs 2 0.1uf lc output filter lc output filter load gain select control gain select osc illator pwm pwm gain select standby control protection circuit bridge h bridge h lin+ lin- g0 g1 rin+ rin- stbyl stbyr lout+ d2 a2 a3 a4 d3 d4 c4 c3 b3 b4 c1 d1 b2 c2 b1 a1 lout- rout+ rout- pvcc pgnd agnd avcc ts2012 cin cin left in+ input capacitors are optional left in- differential left input cin cin right in+ right in- differential right input standby control vcc cs 1 1uf cs 2 0.1uf gain select control gain select osc illator pwm pwm gain select standby control protection circuit bridge h bridge h lin+ lin- g0 g1 rin+ rin- stbyl stbyr lout+ d2 a2 a3 a4 d3 d4 c4 c3 b3 b4 c1 d1 b2 c2 b1 a1 lout- rout+ rout- pvcc pgnd agnd avcc
typical application TS2012EI 6/32 docid026152 rev 1 table 4. external component description components functional description c s1 , c s2 supply capacitor that provides power supply filtering. c in input coupling capacitors (optional) that block the dc voltage at the amplifier input terminal. the capacitors also form a high pass filter with z in (f cl = 1 / (2 x ? x z in x c in )). be aware that value of z in is changing with gain setting. table 5. pin description pin number pin name description a1 lin+ left channel positive differential input a2 pvcc power supply voltage a3 lout+ left channel positive output a4 lout- left channel negative output b1 lin- left channel negative differential input b2 g1 gain select pin (msb) b3 stbyr standby pin (active low) for right channel output b4 stbyl standby pin (active low) for left channel output c1 rin- right channel negative differential input c2 g0 gain select pin (lsb) c3 agnd analog ground c4 pgnd power ground d1 rin+ right channel positive differential input d2 avcc analog supply voltage d3 rout+ right channel positive output d4 rout- right channel negative output
docid026152 rev 1 7/32 TS2012EI electrical characteristics 32 3 electrical characteristics 3.1 electrical characteristics tables table 6. v cc = +5 v, gnd = 0 v, v ic =2.5v, t amb = 25 c (unless otherwise specified) symbol parameters and test conditions min. typ. max. unit i cc supply current no input signal, no load, both channels 57ma i stby standby current no input signal, v stby = gnd 12a v oo output offset voltage floating inputs, g = 6 db, r l = 8 ? 25 mv p o output power thd + n = 1% max, f = 1 khz, r l = 4 ? thd + n = 1% max, f = 1 khz, r l = 8 ? thd + n = 10% max, f = 1 khz, r l = 4 ? thd + n = 10% max, f = 1 khz, r l = 8 ? 1.85 1.15 2.5 1.6 w thd + n total harmonic distortion + noise p o = 0.8 w, g = 6 db, f =1 khz, r l = 8 ? 0.5 % efficiency efficiency per channel p o = 1.85 w, r l = 4 ?? +15h p o = 1.16 w, r l = 8 ? +15h 78 88 % psrr power supply rejection ratio with inputs grounded c in =1f (1) ,f = 217 hz, r l = 8 ??? gain = 6 db ? v ripple = 200 mv pp 65 db crosstalk channel separation p o = 0.9 w, g = 6 db, f =1 khz, r l = 8 ? 90 db cmrr common mode rejection ratio c in = 1 f, f = 217 hz, r l = 8 ??? gain = 6 db ? ? vicm = 200 mv pp 63 db gain gain value with no load g1 = g0 = v il g1 = v il and g0 = v ih g1 = v ih and g0 = v il g1 = g0 = v ih 5.5 11.5 17.5 23.5 6 12 18 24 6.5 12.5 18.5 24.5 db z in single-ended input impedance referred to ground gain = 6 db gain = 12 db gain = 18 db gain = 24 db 24 24 12 6 30 30 15 7.5 36 36 18 9 k ? f pwm pulse width modulator base frequency 190 280 370 khz
electrical characteristics TS2012EI 8/32 docid026152 rev 1 snr signal to noise ratio (a-weighting) p o = 1.1 w, g = 6 db, r l =8 ? 99 db t wu total wake-up time (2) 9 13 16.5 ms t stby standby time (2) 11 15.8 20 ms v n output voltage noise f = 20 hz to 20 khz, r l =8 ? unweighted (filterless, g = 6 db) a-weighted (filterless, g = 6 db) unweighted (with lc output filter, g = 6 db ? a-weighted (with lc output filter, g = 6 db ? unweighted (filterless, g = 24 db) a-weighted (filterless, g = 24 db) unweighted (with lc output filter, g = 24 db ? a-weighted (with lc output filter, g = 24 db ? 61 31 59 31 87 52 87 53 v rms 1. dynamic measurements - 20*log(rms(v out )/rms(v ripple )). v ripple is the superimposed sinus signal to v cc at f = 217 hz. 2. see section 4.6: wake-up time (t wu ) and shutdown time (t stby ) on page 23 . table 6. v cc = +5 v, gnd = 0 v, v ic = 2.5 v, t amb = 25 c (unless otherwise specified) (continued) symbol parameters and test conditions min. typ. max. unit
docid026152 rev 1 9/32 TS2012EI electrical characteristics 32 table 7. v cc = +3.6 v, gnd = 0 v, v ic =1.8v, t amb = 25 c (unless otherwise specified) symbol parameter min. typ. max. unit i cc supply current no input signal, no load, both channels 3.5 5.5 ma i stby standby current no input signal, v stby = gnd 0.7 2 a v oo output offset voltage floating inputs, g = 6 db, r l = 8 ? 25 mv p o output power thd + n = 1% max, f = 1 khz, r l = 4 ? thd + n = 1% max, f = 1 khz, r l = 8 ? thd + n = 10% max, f = 1 khz, r l = 4 ? thd + n = 10% max, f = 1 khz, r l = 8 ? 0.96 0.63 1.3 0.8 w thd + n total harmonic distortion + noise p o = 0.45 w, g = 6 db, f = 1 khz, r l = 8 ? 0.35 % efficiency efficiency per channel p o = 0.96 w, r l = 4 ?????? p o = 0.63 w, r l = 8 ?????? 78 88 % psrr power supply rejection ratio with inputs grounded c in =1f (1) ,f = 217 hz, r l = 8 ??? gain = 6 db ? v ripple =200mv pp 65 db crosstalk channel separation g = 6 db, f = 1 khz, r l = 8 ? 90 cmrr common mode rejection ratio c in = 1 f, f = 217 hz, r l = 8 ??? gain = 6 db ? ? vicm = 200 mv pp 62 db gain gain value with no load g1 = g0 = v il g1 = v il and g0 = v ih g1 = v ih and g0 = v il g1 = g0 = v ih 5.5 11.5 17.5 23.5 6 12 18 24 6.5 12.5 18.5 24.5 db z in single-ended input impedance referred to ground gain = 6 db gain = 12 db gain = 18 db gain = 24 db 24 24 12 6 30 30 15 7.5 36 36 18 9 k ? f pwm pulse width modulator base frequency 190 280 370 khz snr signal-to-noise ratio (a-weighting) p o = 0.6 w, g = 6 db, r l = 8 ? 96 db t wu total wake-up time (2) 7.5 11.3 15 ms
electrical characteristics TS2012EI 10/32 docid026152 rev 1 t stby standby time (2) 10 13.8 18 ms v n output voltage noise f = 20 hz to 20 khz, r l =8 ? unweighted (filterless, g = 6 db) a-weighted (filterless, g = 6 db) unweighted (with lc output filter, g = 6 db ? a-weighted (with lc output filter, g = 6 db ? unweighted (filterless, g = 24 db) a-weighted (filterless, g = 24 db) unweighted (with lc output filter, g = 24 db ? a-weighted (with lc output filter, g = 24 db ? 54 28 52 27 80 50 79 49 v rms 1. dynamic measurements - 20*log(rms(v out )/rms(v ripple )). v ripple is the superimposed sinus signal to v cc at f = 217 hz. 2. see section 4.6: wake-up time (t wu ) and shutdown time (t stby ) on page 23 . table 7. v cc = +3.6 v, gnd = 0 v, v ic =1.8v, t amb = 25 c (unless otherwise specified) (continued) symbol parameter min. typ. max. unit
docid026152 rev 1 11/32 TS2012EI electrical characteristics 32 table 8. v cc = +2.5 v, gnd = 0 v, v ic = 1.25 v, t amb = 25 c (unless otherwise specified) symbol parameter min. typ. max. unit i cc supply current no input signal, no load, both channels 2.8 4 ma i stby standby current no input signal, v stby = gnd 0.45 2 a v oo output offset voltage floating inputs, g = 6 db, r l = 8 ? 25 mv p o output power thd + n = 1% max, f = 1 khz, r l = 4 ? thd + n = 1% max, f = 1 khz, r l = 8 ? thd + n = 10% max, f = 1 khz, r l = 4 ? thd + n = 10% max, f = 1 khz, r l = 8 ? 0.45 0.3 0.6 0.38 w thd + n total harmonic distortion + noise p o = 0.2 w, g = 6 db, f = 1 khz, r l =8 ? 0.2 % efficiency efficiency per channel p o = 0.45 w, r l = 4 ? +15h p o = 0.3 w, r l = 8 ? +15h 78 87 % psrr power supply rejection ratio with inputs grounded c in =1f (1) ,f = 217 hz, r l = 8 ??? gain = 6 db ? v ripple =200mv pp 65 db crosstalk channel separation g = 6 db, f = 1 khz, r l =8 ? 90 cmrr common mode rejection ratio c in = 1 f, f = 217 hz, r l = 8 ??? gain = 6 db ? ? vicm = 200 mv pp 62 db gain gain value with no load g1 = g0 = v il g1 = v il and g0 = v ih g1 = v ih and g0 = v il g1 = g0 = v ih 5.5 11.5 17.5 23.5 6 12 18 24 6.5 12.5 18.5 24.5 db z in single-ended input impedance referred to ground gain = 6 db gain = 12 db gain = 18 db gain = 24 db 24 24 12 6 30 30 15 7.5 36 36 18 9 k ? f pwm pulse width modulator base frequency 190 280 370 khz snr signal-to-noise ratio (a-weighting) p o = 0.28 w, g = 6 db, r l = 8 ? 93 db t wu total wake-up time (2) 37.812 ms
electrical characteristics TS2012EI 12/32 docid026152 rev 1 t stby standby time (2) 81216ms v n output voltage noise f = 20 hz to 20 khz, r l =8 ? unweighted (filterless, g = 6 db) a-weighted (filterless, g = 6 db) unweighted (with lc output filter, g = 6 db ? a-weighted (with lc output filter, g = 6 db ? unweighted (filterless, g = 24 db) a-weighted (filterless, g = 24 db) unweighted (with lc output filter, g = 24 db ? a-weighted (with lc output filter, g = 24 db ? 51 26 49 26 77 49 76 48 v rms 1. dynamic measurements - 20*log(rms(v out )/rms(v ripple )). v ripple is the superimposed sinus signal to v cc at f = 217 hz. 2. see section 4.6: wake-up time (t wu ) and shutdown time (t stby ) on page 23 . table 8. v cc = +2.5 v, gnd = 0 v, v ic = 1.25 v, t amb = 25 c (unless otherwise specified) (continued) symbol parameter min. typ. max. unit
docid026152 rev 1 13/32 TS2012EI electrical characteristics 32 3.2 electrical characteristic curves the graphs shown in this section use the following abbreviations. ? r l + 15 h or 30 h = pure resistor + very low series resistance inductor. ? filter = lc output filter (1 f+ 30 h for 4 ?? and 0.5 f+15 h for 8 ? ). all measurements are done with c s1 =1 f and c s2 =100 nf ( figure 2 ), except for the psrr where c s1 is removed ( figure 3 ). figure 2. test diagram for measurements vcc cin cin cs 1 1/2 ts2012 cs 2 100nf in+ in- 15 h or 30 h ?? or lc filter out+ out- 1 f ? ? 4 or 8 rl 5th order 50khz low-pass filter audio measurement b a nd wi t h < 30 k hz gnd gnd gnd
electrical characteristics TS2012EI 14/32 docid026152 rev 1 figure 3. test diagram for psrr measurements vcc cin cin 1/2 ts2012 cs 2 100nf in+ in- 15 h or 30 h ?? or lc filter out+ out- ? 4 or 8 rl 5th order 50khz low-pass filter rms selective measurement bandwith =1% of fmeas gnd gnd gnd 1 f ? 1 f ? gnd 5th order 50khz low-pass filter reference 20hz to 20khz vripple vcc
docid026152 rev 1 15/32 TS2012EI electrical characteristics 32 figure 4. current consumption vs. power supply voltage figure 5. current consumption vs. standby voltage (one channel) 012345 0 1 2 3 4 5 6 one channel active no load tamb = 25 ? c current consumption (ma) power supply voltage (v) both channels active 012345 0 1 2 3 vcc=2.5v vcc=3.6v one channel active current consumption (ma) standby voltage (v) no load tamb = 25 ? c vcc=5v figure 6. efficiency vs. output power (one channel) figure 7. efficiency vs. output power (one channel) 0.0 0.4 0.8 1.2 1.6 2.0 2.4 0 20 40 60 80 100 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 power dissipation vcc = 5v rl = 4 ? + 16 ? h f = 1khz thd+n ?? 10% efficiency (%) output power (w) efficiency dissipated power (w) 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 0 20 40 60 80 100 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 power dissipation vcc = 3.6v rl = 4 ? + 16 ? h f = 1khz thd+n ?? 10% efficiency (%) output power (w) efficiency dissipated power (w) figure 8. efficiency vs. output power (one channel) figure 9. efficiency vs. output power (one channel) 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0 20 40 60 80 100 0.00 0.02 0.04 0.06 0.08 0.10 0.12 0.14 0.16 0.18 0.20 0.22 0.24 power dissipation vcc = 2.5v rl = 4 ? + 16 ? h f = 1khz thd+n ?? 10% efficiency (%) output power (w) efficiency dissipated power (w) 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 0 20 40 60 80 100 0.00 0.02 0.04 0.06 0.08 0.10 0.12 0.14 0.16 0.18 0.20 0.22 0.24 0.26 0.28 0.30 power dissipation vcc = 5v rl = 8 ? + 16 ? h f = 1khz thd+n ?? 10% efficiency (%) output power (w) efficiency dissipated power (w)
electrical characteristics TS2012EI 16/32 docid026152 rev 1 figure 10. efficiency vs. output power (one channel) figure 11. efficiency vs. output power (one channel) 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 0 20 40 60 80 100 0.00 0.05 0.10 0.15 power dissipation vcc = 3.6v rl = 8 ? + 16 ? h f = 1khz thd+n ?? 10% efficiency (%) output power (w) efficiency dissipated power (w) 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0 20 40 60 80 100 0.00 0.02 0.04 0.06 0.08 power dissipation vcc = 2.5v rl = 8 ? + 16 ? h f = 1khz thd+n ?? 10% efficiency (%) output power (w) efficiency dissipated power (w) figure 12. psrr vs. frequency figure 13. psrr vs. frequency 100 1000 10000 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 psrr (db) frequency (hz) vcc = 5v vripple = 200mvpp cin = 10 ? f rl = 8 ? + 16 ? h tamb = 25 ? c g=+12db g=+6db g=+18db g=+24db 100 1000 10000 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 g=+12db g=+6db g=+18db psrr (db) frequency (hz) vcc = 3.6v vripple = 200mvpp cin = 10 ? f rl = 8 ? + 16 ? h tamb = 25 ? c g=+24db figure 14. psrr vs. frequency figure 15. psrr vs. common mode input voltage 100 1000 10000 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 psrr (db) frequency (hz) vcc = 2.5v vripple = 200mvpp cin = 10 ? f rl = 8 ? + 16 ? h tamb = 25 ? c g=+12db g=+6db g=+18db g=+24db 012345 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 g=+24db g=+18db g=+12db vcc = 5v vripple = 200mvpp f = 217hz rl = 8 ? + 16 ? h tamb = 25 ? c g=+6db psrr (db) common mode input voltage (v)
docid026152 rev 1 17/32 TS2012EI electrical characteristics 32 figure 16. psrr vs. common mode input voltage figure 17. psrr vs. common mode input voltage 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 g=+24db g=+18db g=+12db vcc = 3.6v vripple = 200mvpp f = 217hz rl = 8 ? + 16 ? h tamb = 25c g=+6db psrr (db) common mode input voltage (v) 0.0 0.5 1.0 1.5 2.0 2.5 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 g=+24db g=+18db g=+12db vcc = 2.5v vripple = 200mvpp f = 217hz rl = 8 ? + 16 ? h tamb = 25 ? c g=+6db psrr (db) common mode input voltage (v) figure 18. cmrr vs. frequency figure 19. cmrr vs. frequency 100 1000 10000 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 g=+24db g=+18db g=+12db cmrr (db) frequency (hz) vcc = 5v vripple = 200mvpp cin = 10 ? f rl = 8 ? + 15 ? h tamb = 25 ? c g=+6db 100 1000 10000 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 g=+24db g=+18db g=+12db cmrr (db) frequency (hz) vcc = 3.6v vripple = 200mvpp cin = 10 ? f rl = 8 ? + 15 ? h tamb = 25 ? c g=+6db figure 20. cmrr vs. frequency figure 21. cmrr vs. common mode input voltage 100 1000 10000 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 g=+24db g=+18db g=+12db cmrr (db) frequency (hz) vcc = 2.5v vripple = 200mvpp cin = 10 ? f rl = 8 ? + 15 ? h tamb = 25 ? c g=+6db 012345 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 vcc=3.6v vripple = 200mvpp f = 217hz, g = +6db rl ? 8 ? + 15 ? h tamb = 25 ? c vcc=2.5v cmrr (db) common mode input voltage (v) vcc=5v
electrical characteristics TS2012EI 18/32 docid026152 rev 1 figure 22. cmrr vs. common mode input voltage figure 23. cmrr vs. common mode input voltage 012345 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 vcc=3.6v vripple = 200mvpp f = 217hz, g = +12db rl ? 8 ? + 15 ? h tamb = 25 ? c vcc=2.5v cmrr (db) common mode input voltage (v) vcc=5v 012345 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 vcc=3.6v vripple = 200mvpp f = 217hz, g = +18db rl ? 8 ? + 15 ? h tamb = 25 ? c vcc=2.5v cmrr (db) common mode input voltage (v) vcc=5v figure 24. cmrr vs. common mode input voltage figure 25. thd+n vs. output power 012345 -80 -70 -60 -50 -40 -30 -20 -10 0 vcc=3.6v vripple = 200mvpp f = 217hz, g = +24db rl ? 8 ? + 15 ? h tamb = 25 ? c vcc=2.5v cmrr (db) common mode input voltage (v) vcc=5v 0.01 0.1 1 0.01 0.1 1 10 vcc=2.5v vcc=3.6v f = 1khz rl = 4 ? + 15 ? h g = +6db bw < 30khz tamb = 25 ? c thd + n (%) output power (w) vcc=5v figure 26. thd+n vs. output power figure 27. thd+n vs. frequency 0.01 0.1 1 0.01 0.1 1 10 vcc=2.5v vcc=3.6v f = 1khz rl = 8 ? + 15 ? h g = +6db bw < 30khz tamb = 25 ? c thd + n (%) output power (w) vcc=5v 100 1000 10000 0.01 0.1 1 10 vcc=2.5v, po=300mw vcc=3.6v, po=700mw vcc=5v, po=1300mw thd + n (%) frequency (hz) rl = 4 ? + 15 ? h g = +6db bw < 30khz tamb = 25 ? c
docid026152 rev 1 19/32 TS2012EI electrical characteristics 32 figure 28. thd+n vs. frequency figure 29. crosstalk vs. frequency 100 1000 10000 0.01 0.1 1 10 vcc=2.5v, po=200mw vcc=3.6v, po=450mw vcc=5v, po=800mw thd + n (%) frequency (hz) rl = 8 ? + 15 ? h g = +6db bw < 30khz tamb = 25 ? c 100 1000 10000 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 vcc=2.5v vcc=3.6v crosstalk level (db) frequency (hz) rl = 4 ? + 15 ? h cin = 1 ? f g = +6db tamb = 25 ? c vcc=5v figure 30. crosstalk vs. frequency figur e 31. output power vs. power supply voltage 100 1000 10000 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 vcc=2.5v vcc=3.6v crosstalk level (db) frequency (hz) rl = 8 ? + 15 ? h cin = 1 ? f g = +6db tamb = 25 ? c vcc=5v 2.5 3.0 3.5 4.0 4.5 5.0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 rl=8 ?? +15 ? h rl=4 ?? +15 ? h f = 1khz bw < 30khz tamb = 25 ? c output power at 1% thd + n (mw) supply voltage (v) figure 32. output power vs. power supply voltage figure 33. power derating curves 2.5 3.0 3.5 4.0 4.5 5.0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 rl=8 ?? +15 ? h rl=4 ?? +15 ? h f = 1khz bw < 30khz tamb = 25 ? c output power at 10% thd + n (w) vcc (v) 0 255075100125150 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 with a 4-layer pcb flip-chip package power dissipation (w) ambiant temperature ( ? c) no heat sink amr value
electrical characteristics TS2012EI 20/32 docid026152 rev 1 figure 34. startup and shutdown phase v cc =5v, g=6db, c in = 1 f, inputs grounded figure 35. startup and shutdown phase v cc =5v, g=6db, c in =1f, v in =2v pp , f=500hz out+ out- standby out+ - out- out+ - out- standby out+ out-
docid026152 rev 1 21/32 TS2012EI application information 32 4 application information 4.1 differential configuration principle the TS2012EI is a monolithic fu lly-differential inpu t/output class d power amplifier. the TS2012EI also includes a common-mode feedback loop that controls t he output bias value to average it at v cc /2 for any dc common mo de input voltage. this allows the device to always have a maximum output voltage swing, and by consequence, maximize the output power. moreover, as the load is connected differentially compared with a single-ended topology, the output is four times higher for the same power supply voltage. the advantages of a full-differential amplifier are: ? high psrr (power supp ly rejection ratio), ? high common mode noise rejection, ? virtually zero pop without additional circuitry, giving a faster start-up time compared to conventional single-ended input amplifiers, ? easier interfacing with differential output audio dacs, ? no input coupling capacitors required thanks to the common mode feedback loop. 4.2 gain settings in the flat region of the freq uency-response curve (no input coupling capacitor or internal feedback loop + load effect), the differential gain can be set to 6, 12 18, or 24 db, depending on the logic level of the g0 and g1 pins, as shown in table 9 . note: between pins g0, g1 and gnd there is an internal 300 k ? (+/-20%) resistor. when the pins are floating, the gain is 6 db. in full standby (left and right channels off), these resistors are disconnected (hiz input). 4.3 common mode feedback loop limitations as explained previously, the common mode fe edback loop allows the output dc bias voltage to be averaged at v cc /2 for any dc common mode bias input voltage. due to the v ic limitation of the input stage (see table 3: operating conditions on page 4 ), the common mode feedback loop can fulfill its role only within the defined range. table 9. gain settings with g0 and g1 pins g1 g0 gain (db) gain (v/v) 0062 01124 10188 1 1 24 16
application information TS2012EI 22/32 docid026152 rev 1 4.4 low frequency response if a low frequency bandwid th limitation is required, it is possible to use input coupling capacitors. in the low-frequency region, the input coupling capacitor c in starts to have an effect. c in forms, with the input impedance z in , a first order high-pass filter with a -3 db cut- off frequency (see table 6 to table 8 ). so, for a desired cut-off frequency f cl , c in is calculated as follows. with f cl in hz, z in in ? and c in in f. the input impedance z in is for the whole power supply voltage range and it changes with the gain setting. there is also a tolerance around the typical values (see table 6 to table 8 ). figure 36. cut-off frequency vs. input capacitor f cl 1 2 ? z in c in ?? ? ------------------------------------ = c in 1 2 ? z in f cl ?? ? ------------------------------------- - = 0.1 1 1 10 100 g=24db zin=7.5k ? typ. g=18db zin=15k ? typ. g=6db, g=12db zin=30k ? typ. tamb=25 ? c low -3db cut off frequency (hz) input capacitor cin ( ? f)
docid026152 rev 1 23/32 TS2012EI application information 32 4.5 decoupling of the circuit power supply capacitors, referred to as c s1 and c s2 , are needed to correctly bypass the TS2012EI. the TS2012EI has a typical switching frequency of 280 khz and an output fall and rise time of approximately 5 ns. due to these very fast transients, careful decoupling is mandatory. a 1 f ceramic capacitor (c s1 ) between pvcc and pgnd and one additional ceramic capacitor 0.1 f (c s2 ) are enough. a 1 f capacitor must be located as close as possible to the device pvcc pin in order to avoid any extr a parasitic inductance or resistance created by a long track wire. parasitic loop inductance, in relation with di/dt, introduces overvoltage that decreases the global efficiency of the devi ce and may cause, if this parasitic inductance is too high, a breakdown of the TS2012EI. for filtering low-frequency noise signals on the power line, you can use a c s1 capacitor of 4.7 f or more. in addition, even if a ceramic capacitor ha s an adequate high frequency esr (equivalent series resistance) value, its cu rrent capability is also importa nt. a size of 0603 is a good compromise, particularly when a 4 ? load is used. another important parameter is the rated voltage of the capacitor. a 1 f/6.3 v capacitor used at 5 v, loses about 50% of its value. with a power supply voltage of 5 v, the decoupling value, instead of 1 f, could be reduced to 0.5 f. as c s has particular influence on the thd+n in the medium-to-high frequency region , this capacitor variat ion becomes decisive. in addition, less decoupling means higher over shoots, which can be problematic if they reach the power supply amr value (6 v). 4.6 wake-up time (t wu ) and shutdown time (t stby ) during the wake-up sequence when the standby is released to set the device on, there is a delay. the wake-up sequence of the TS2012EI consists of two phases. during the first phase t wu-a , a digitally-generated delay, mutes the outputs. then, the gain increasing phase t wu-a begins. the gain increases smoothly from the mute state to the preset gain selected by the digital pins g0 and g1. this startup sequence avoids any pop noise during startup of the amplifier. refer to figure 37: wake-up phase
application information TS2012EI 24/32 docid026152 rev 1 figure 37. wake-up phase when the standby command is set, the time required to set the output stage to high impedance and to put the internal circuitry in shutdown mode is called the standby time. this time is used to decrease the gain from it s nominal value set by the digital pins g0 and g1 to mute and avoid any pop noise during shutdown. the gain decreases smoothly until the outputs are muted ( figure 38 ). figure 38. shutdown phase preset gain gain increasing t wu-a t wu t wu-b stby mute time time gain stby level stby lo hi g = 6db g = 12db g = 18db g = 24db mute preset gain t stby stby time time gain stby level gain decreasing lo hi g = 6db g = 12db g = 18db g = 24db mute stby mute
docid026152 rev 1 25/32 TS2012EI application information 32 4.7 consumption in shutdown mode between the shutdown pin and gnd there is an internal 300 k ? (+-/20%) resistor. this resistor forces the TS2012EI to be in shut down when the shutdown input is left floating. however, this resistor also introduces addi tional shutdown power consumption if the shutdown pin voltage is not at 0 v. with a 0.4 v shutdown voltage pin for example, you must add 0.4 v/300 k ? = 1.3 a typical (0.4 v/240 k ? = 1.66 a maximum) for each shutdown pin to the standby current specified in table 6 to table 8 . of course, this current will be provided by the external control device for the standby pins. 4.8 single-ended input configuration it is possible to use the TS2012EI in a single-ended input configuration. however, input coupling capacitors are mandatory in this configuration. figure 39 shows a typical single- ended input application. figure 39. typical application fo r single-ended input configuration ts2012 left speaker right speaker cin cin left input cin cin right input standby control vcc cs 1 1uf vcc cs 2 0.1uf gain select control gain select oscillator pwm pwm gain select standby control protection circuit bridge h bridge h lin+ lin- g0 g1 rin+ rin- stbyl stbyr lout+ d2 a2 a3 a4 d3 d4 c4 c3 b3 b4 c1 d1 b2 c2 b1 a1 lout- rout+ rout- pvcc pgnd agnd avcc
application information TS2012EI 26/32 docid026152 rev 1 4.9 output filter considerations the TS2012EI is designed to operate without an output filter. however, due to very sharp transients on the TS2012EI output, emi-radiated emissions may cause some standard compliance issues. these emi standard compliance issues can appear if the distance between the TS2012EI outputs and loudspeaker terminal are long (typically more than 50 mm, or 100 mm in both directions, to the speaker terminals). because the pcb layout and internal equipment device are different for each configuration, it is difficult to provide a one-size-fits-all solution. however, to decrease the probability of emi is sues, there are several simple rules to follow. ? reduce, as much as possible, the distance between the TS2012EI output pins and the speaker terminals. ? use a ground plane to "shield" sensitive wires. ? place, as close as possible to the TS2012EI and in series with each output, a ferrite bead with a rated current of at least 2.5 a and an impedance greater than 50 ?? at frequencies above 30 mhz. if, after testing, these ferrite beads are not necessary, replace them by a short-circuit. ? allow extra footprint to place, if necessary, a capacitor to short perturbations to ground ( figure 40 ). figure 40. ferrite chip bead placement in the case where the distance between the ts 2012ei output and the speaker terminals is too long, it is possible to have low frequency emi issues due to the fact that the typical operating frequency is 280 khz. in this configurat ion, it is necessary to use the output filter represented in figure 1 on page 5 as close as possible to the TS2012EI. 4.10 short-circuit protection the TS2012EI includes output short-circuit pr otection. this protecti on prevents the device from being damaged in case of fault conditions on the amplifier outputs. when a channel is in operating mode and a shor t-circuit occurs between two outputs of the channel or between an output and ground, the s hort-circuit protection detects this situation and puts the appropriate channel into standby. to put the channel back into operating mode, it is necessary to put the channel?s standby pin to logical lo, and then back again to logical hi and wake up the channel. to speaker about 100pf gnd ferrite chip bead from output
docid026152 rev 1 27/32 TS2012EI application information 32 4.11 thermal shutdown the TS2012EI device has an internal thermal shutdown protection in the event of extreme temperatures to protect the device from over heating. thermal shutdown is active when the device reaches 150 c. when the temperature decr eases to safe levels, the circuit switches back to normal operation.
package information TS2012EI 28/32 docid026152 rev 1 5 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions a nd product status are available at: www.st.com . ecopack ? is an st trademark. figure 41. flip chip 16 package mechanical drawing die size: 2.07 x 2.07 mm 50 m die height (including bumps): 600 m bump diameter: 315 m 50m bump diameter before reflow: 300 m 10m bump height: 250 m 40m die height: 350 m 20m pitch: 500 m 50m bump coplanarity: 60 m max optional*: back coating height: 40 m 500 ? m 2.1 mm 2.1 mm 600 ? m 40 ? m* g1 inl+ 250 ? m 500 ? m 2.1 mm 2.1 mm 600 ? m 40 ? m* g1 inl+ 250 ? m 2.07mm 2.07 mm
docid026152 rev 1 29/32 TS2012EI package information 32 figure 42. pinout (top view) figure 43. marking (top view) 1 4 3 2 ad c b g1 inl+ lin+ lin- rin- rin+ pvcc g1 g0 avcc lout+ stdbyr agnd rout+ rout- pgnd stdbyl lout- 1 4 3 2 ad c b g1 inl+ lin+ lin- rin- rin+ pvcc g1 g0 avcc lout+ stdbyr agnd rout+ rout- pgnd stdbyl lout- g1 inl+ lin+ lin- rin- rin+ pvcc g1 g0 avcc lout+ stdbyr agnd rout+ rout- pgnd stdbyl lout- k0 x yww e k0 x yww e ? st logo ? symbol for lead-free: e ? two first product codes: k0 ? third x: assembly line plant code ? three-digit date code: y for year - ww for week ? the dot indicates pin a1
package information TS2012EI 30/32 docid026152 rev 1 figure 44. tape and reel schematics (top view) figure 45. recommended footprint user direction of feed 8 die size x + 70m die size y + 70m 4 4 all dimensions are in mm a 1 a 1 user direction of feed 8 die size x + 70m die size y + 70m 4 4 all dimensions are in mm a 1 a 1 150 ? m min. 500 ? m 500 ? m 500 ? m 500 ? m ? =250 ? m ? =400 ? m typ. 75m min. 100 ? m max. track non solder mask opening ? =340 ? m min. pad in cu 18 ? m with flash niau (2-6 ? m, 0.2 ? m max.) 150 ? m min. 500 ? m 500 ? m 500 ? m 500 ? m ? =250 ? m ? =400 ? m typ. 75m min. 100 ? m max. track non solder mask opening ? =340 ? m min. pad in cu 18 ? m with flash niau (2-6 ? m, 0.2 ? m max.)
docid026152 rev 1 31/32 TS2012EI revision history 32 6 revision history table 10. document revision history date revision changes 01-apr-2014 1 initial release.
TS2012EI 32/32 docid026152 rev 1 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. st products are not designed or authorized for use in: (a) safety critical applications such as life supporting, active implanted devices or systems wi th product functional safety requirements; (b) aeronautic applications; (c) automotive applications or environments, and/or (d) aerospace applications or environments. where st products are not designed for such use, the purchaser shall use products at purchaser?s sole risk, even if st has been informed in writing of such usage, unless a product is expressly designated by st as being intended for ?automotive, automotive safety or medical? industry domains according to st product design specifications. products formally escc, qml or jan qualified are deemed suitable for use in aerospace by the corresponding governmental agency. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2014 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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